View SY89430_74799.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

5V/3.3V PROGRAMMABLE FREQUENCY SYNTHESIZER (50MHz to 950MHz)
FEATURES
s s s s s s s s 5V and 3.3V power supply options 50MHz to 950MHz differential PECL outputs 25ps peak-to-peak output jitter Minimal frequency over-shoot Synthesized architecture Serial 3 wire interface Parallel interface for power-on Internal quartz reference oscillator driven by quartz crystal s External loop filter optimizes performance/cost s Applications note (AN-07) for ease of design-ins s Available in 28-pin PLCC and SOIC packages
ClockWorksTM SY89430V
DESCRIPTION
The SY89430V is a general purpose, synthesized clock source targeting applications that require both serial and parallel interfaces. Its internal VCO will operate over a range of frequencies from 400MHz to 950MHz. The differential PECL output can be configured to be the VCO frequency divided by 1, 2, 4 or 8. With the output configured to divide the VCO frequency by 2, and with a 16MHz external quartz crystal used to provide the reference frequency, the output frequency can be specified in 1MHz steps.
PIN CONFIGURATION
GND (TTL) VCC (TTL)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23
VCC_OUT
M[0] M[1] M[2]
P_LOAD VCC1 XTAL2 XTAL1 LOOP_REF LOOP_FILTER VCC_QUIET S_LOAD S_DATA S_CLOCK VCC_OUT FOUT FOUT GND
FOUT
FOUT GND
25 24 23 22 21 20 19
TEST
S_CLOCK S_DATA S_LOAD VCC_QUIET LOOP _FILTER LOOP_REF XTAL1
26 27 28 1 2 3 4 5 6 7 8 9 10 11
18 17
N[1] N[0] M[8] M[7] M[6] M[5] M[4]
M[3] M[4] M[5] M[6] M[7] M[8]
PLCC TOP VIEW
16 15 14 13 12
TOP VIEW SOIC Z28-1
22 21 20 19 18 17 16 15
P_LOAD M[0]
M[1]
M[2]
XTAL2
VCC1
M[3]
N[0] N[1] GND (TTL) TEST
APPLICATIONS
s s s s s s s s Workstations Advanced communications High end consumer High-performance computing RISC CPU clock Graphics pixel clock Test equipment Other high-performance processor-based applications
VCC (TTL)
Rev.: E
Amendment: /0
1
Issue Date: May 2000
Micrel
ClockWorksTM SY89430V
BLOCK DIAGRAM
+3.3V or +5.0V
/8
FREF
PLL
PHASE DETECTOR VCO
10-25MHz Fundamental Crystal
PECL
OSC /M
400 - 950 MHz
/N
FOUT
3 WIRE INTERFACE
SERIAL PARALLEL
INTERFACE LOGIC
TEST
CONFIG INFO
DETAILED BLOCK DIAGRAM
150 3300pF 2 LOOP_FILTER FREF 3
0.47F
+3.3V or +5.0V 1 VCC_QUIET
+3.3V or +5.0V 6, 21 VCC1
LOOP_REF
/8
PHASE DETECTOR VCO 400 - 950 MHz T110 /N (2,4,8,1) VCC_OUT +3.3V or +5.0V 25 24 23 FOUT FOUT
4 10-25MHz Fundamental Crystal XTAL1 OSC 5 XTAL2
L = LATCH H = Transparent
1
0
9-BIT / M COUNTER
FOUT / 4 -- 7
28 S_LOAD
LATCH
LATCH
S_CLOCK / M -- 6
LATCH P_LOAD 7 0 1
0 1
LOW -- 5 FOUT -- 4 /M-- 3 FREF -- 2
20
TEST
S_DATA S_CLOCK
27 26
9-BIT SR
2-BIT SR
3-BIT SR
HIGH -- 1 0
8 -> 16 9 M[8:0]
17,18 2 N[1:0]
19,22
NOTE: Pin numbers reference PLCC pinout.
2
Micrel
ClockWorksTM SY89430V
PIN DESCRIPTIONS
INPUTS XTAL1, XTAL2 These pins form an oscillator when connected to an external crystal. The crystal is series resonant. S_LOAD This TTL pin loads the configuration latches with the contents of the shift registers. The latches will be transparent when this signal is HIGH; thus, the register data must be stable on the HIGH-to-LOW transition of S_LOAD for proper operation. S_DATA This TTL pin is the input to the serial configuration shift registers. S_CLOCK This TTL pin clocks the serial configuration shift registers. On the rising edge of this signal, data from S_DATA is sampled. P_LOAD This TTL pin loads the configuration latches with the contents of the parallel inputs. The latches will be transparent when this signal is LOW; thus, the parallel data must be stable on the LOW-to-HIGH transition of P_LOAD for proper operation. M[8:0] These TTL pins are used to configure the PLL loop divider. They are sampled on the LOW-to-HIGH transition of P_LOAD. M[8] is the MSB, M[0] is the LSB. The binary count on the M pins equates to the divide-by value for the PLL. N[1:0] These TTL pins are used to configure the output divider modulus. They are sampled on the LOW-to-HIGH transition of P_LOAD.
N[1:0] 00 01 10 11 Output Division 2 4 8 1
OUTPUTS FOUT, FOUT These differential positive-referenced ECL signals (PECL) are the output of the synthesizer. TEST The function of this TTL output is determined by the serial configuration bits T[2:0]. POWER VCC1 This is the positive supply for the chip and is normally connected to +3.3V or +5.0V. VCC_OUT This is the positive reference for the PECL outputs, FOUT and FOUT. It is constrained to be less than or equal to VCC1. VCC_QUIET This is the positive supply for the PLL and should be as noisefree as possible for low-jitter operation. GND These pins are the negative supply for the chip and are normally all connected to ground. OTHER LOOP_FILTER This is an analog I/O pin that provides the loop filter for the PLL. LOOP_REF This is an analog I/O pin that provides a reference voltage for the PLL.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VCC VI IOUT Tstore TA
NOTE:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may affect device reliability.
Parameter Power Supply Voltage Input Voltage Output Source Storage Temperature Operating Temperature Continuous Surge
Value -0.5 to +7.0 -0.5 to +7.0 50 100 -65 to +150 -0 to +75
Unit V V mA C C
3
Micrel
ClockWorksTM SY89430V
WITH 16MHZ INPUT
VCO Frequency (MHz) 400 402 404 406 * * * 944 946 948 950 256 M8 0 0 0 0 * * * 1 1 1 1 128 M7 1 1 1 1 * * * 1 1 1 1 64 M6 1 1 1 1 * * * 1 1 1 1 32 M5 0 0 0 0 * * * 0 0 0 0 16 M4 0 0 0 0 * * * 1 1 1 1 8 M3 1 1 1 1 * * * 1 1 1 1 4 M2 0 0 0 0 * * * 0 0 0 0 2 M1 0 0 1 1 * * * 0 0 1 1 1 M0 0 1 0 1 * * * 0 1 0 1
M Count 200 201 202 203 * * * 472 473 474 475
FUNCTIONAL DESCRIPTION
The internal oscillator uses the external quartz crystal as the basis of its frequency reference. The output of the reference oscillator is divided by eight before being sent to the phase detector. With a 16MHz crystal, this provides a reference frequency of 2MHz. The VCO within the PLL operates over a range of 400- 950MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The output of this loop divider is also applied to the phase detector. The phase detector and loop filter force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve loop lock. External loop filter components are utilized to allow for optimal phase jitter performance. The output of the VCO is also passed through an output divider before being sent to the PECL output driver. The output divider is configured through either the serial or the parallel interfaces and can provide one of four divider ratios (1, 2, 4 or 8). This divider extends the performance of the part while providing a 50% duty cycle. The output driver is driven differentially from the output divider and is capable of driving a pair of transmission lines terminated in 50 to VCC -2volts. The positive reference for the output driver is provided by a dedicated power pin (VCC_OUT) to reduce noise induced jitter. The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0] inputs to configure the internal counters. Normally upon system reset, the P_LOAD input is held LOW until sometime after power becomes valid. With S_LOAD held LOW, on the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pull-up resistors are provided on the M[8:0] and N[1:0] inputs to reduce component count. The serial interface logic is implemented with a 14-bit shift register scheme. The register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet set-up and hold timing as specified in the AC parameters section of this data sheet. With P_LOAD held HIGH, the configuration latches will capture the value in the shift register on the HIGH-to-LOW edge of the S_LOAD input. See the programming section for more information. The TEST output reflects various internal node values and is controlled by the T[2:0] bits in the serial data stream. See the programming section for more information.
4
Micrel
ClockWorksTM SY89430V
PROGRAMMING INTERFACE
Programming the device is accomplished by properly configuring the internal dividers to produce the desired frequency at the outputs. The output frequency can be represented by this formula:
FOUT = ( M FXTAL )x 8 N
Where FXTAL is the crystal frequency, M is the loop divider modulus, and N is the output divider modulus. Note that it is possible to select values of M such that the PLL is unable to achieve loop lock. To avoid this, always make sure that M is selected to be 200 M 510 for a 16MHz input reference. M[8:0] and N[1:0] are normally specified once at power-on, through the parallel interface, and then possibly again through the serial interface. This approach allows the designer to bring up the application at one frequency and then change or finetune the clock, as the ability to control the serial interface becomes available. To minimize transients in the frequency domain, the output should be varied in the smallest step size possible.
T2
0 0 0 0 1 1 1 1
T1
0 0 1 1 0 0 1 1
T0
0 1 0 1 0 1 0 1 HIGH FREF
TEST
Data Out - Last Bit SR
FOUT / FOUT FVCO / N FVCO / N FVCO / N FVCO / N FVCO / N FVCO / N S_CLOCK / N FVCO / N
M Counter Output FOUT LOW S_CLOCK / M FOUT / 4
The TEST output provides visibility for one of several internal nodes (as determined by the T[1:0] bits in the serial configuration stream). It is not configurable through the parallel interface. Although it is possible to select the node that represents FOUT, the TTL output may not be able to toggle fast enough for some of the higher output frequencies. The T2, T1, T0 configuration latches are preset to 000 when P_LOAD is low, so that the FOUT outputs are as jitter-free as possible. The serial configuration port can be used to select one of the alternate functions for this pin. The Test register is loaded with the first three bits, the N register with the next two and the M register with the final eight bits of the data stream on the S_DATA input. For each register the most significant bit is loaded first (T2, N1 and M8). When T[2:0] is set to 100 the SY89430V is placed in PLL bypass mode. In this mode the S_CLOCK input is fed directly into the M and N dividers. The N divider drives the FOUT differential pair and the M counter drives the TEST output pin. In this mode the S_CLOCK input could be used for low speed board level functional test or debug. Bypassing the PLL and driving FOUT directly gives the user more control on the test clocks sent through the clock tree (See detailed Block Diagram). Because the S_CLOCK is a TTL level the input frequency is limited to 250MHz or less. This means the fastest the FOUT pin can be toggled via the S_CLOCK is 125MHz as the minimum divide ratio of the N counter is 2. Note that the M counter output on the TEST output will not be a 50% duty cycle due to the way the divider is implemented.
S_CLOCK
S_DATA
T2
First Bit
T1
T0
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
Last Bit
S_LOAD M[8:0] N[1:0]
M,N
P_LOAD
5
Micrel
ClockWorksTM SY89430V
100H ECL DC ELECTRICAL CHARACTERISTICS
VCC1 = VCC_QUIET = VCC_TTL = VCC_OUT = +3.3V to +5.0V 5%; TA = 0C to +75C
Symbol VOH VOL Parameter Output HIGH Voltage Output LOW Voltage Min. VCC_OUT -1.075 VCC_OUT -1.860 Max. VCC_OUT -0.830 VCC_OUT -1.570 Unit V V Condition 50 to VCC_OUT -2V 50 to VCC_OUT -2V
TTL DC ELECTRICAL CHARACTERISTICS
VCC1 = VCC_QUIET = VCC_TTL = VCC_OUT = +3.3V to +5.0V 5%; TA = 0C to +75C
TA = 0C Symbol VIH VIL IIH IIL VIK VOH VOL IOS ICC1 Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Input Clamp Voltage Output HIGH Voltage Output LOW Voltage Output Short Circuit Current Supply Current Typical % of ICC1 VCC1 VCC_OUT VCC_QUIET VCC_TTL Min. 2.0 -- -- -- -- -- -- -- 33% 9% 14% 44% Max. -- 0.8 50 -0.6 -1.2 2.0 0.5 220 TA = +25C Min. 2.0 -- -- -- -- -- -- -- 33% 9% 14% 44% Max. -- 0.8 50 -0.6 -1.2 2.0 0.5 220 TA = +75C Min. 2.0 -- -- -- -- -- -- -- 33% 9% 14% 44% Max. -- 0.8 50 -0.6 -1.2 2.0 0.5 220 Unit V V A mA V V V mA mA mA Condition -- -- VIN = 2.7V VIN = 0.5V IIN = -12mA IOH = -2.0mA IOL = 8mA VOUT = 0V 5.0V 5% 3.3V 5%
-100 (Typ.)
0.91X of 5V Val.
-100 (Typ.)
0.91X of 5V Val.
-100 (Typ.)
0.91X of 5V Val.
AC ELECTRICAL CHARACTERISTICS
VCC1 = VCC_QUIET = VCC_TTL = VCC_OUT = +3.3V to +5.0V 5%; TA = 0C to +75C
TA = 0C Symbol fMAXI fMAXO tLOCK tjitter tS Parameter Maximum Input Frequency
(1)
TA = +25C Min. -- 10 400 50 -- -- 20 20 20 20 20 20 50 50 45 100 Max. 10 25 950 950 10 25 -- -- -- -- -- -- -- -- 55 500
TA = +75C Min. -- 10 400 50 -- -- 20 20 20 20 20 20 50 50 45 100 Max. 10 25 950 950 10 25 -- -- -- -- -- -- -- -- 55 500 Unit MHz MHz ms ps ns Test output static Condition Fundamental Cyrstal
Min. S_CLOCK Xtal Oscillator -- 10 400 50 -- -- 20 20 20 20 20 20 50 50 45 FOUT 100
Max. 10 25 950 950 10 25 -- -- -- -- -- -- -- -- 55 500
Maximum Output Frequency VCO (Internal) FOUT Maximum PLL Lock Time Cycle-to-Cycle Jitter (Peak-toPeak) Setup Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to P_LOAD S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to P_LOAD S_LOAD P_LOAD
tH
Hold Time
ns
tpw(MIN) tDC tr tf
Minimum Pulse Width FOUT Duty Cycle Output Rise/Fall 20% to 80%
ns % ps
NOTE: 1. 10MHz is the maximum frequency to load the feedback divide registers. S_CLOCK can be switched at high frequencies when used as a test clock in TEST_MODE 6.
6
Micrel
ClockWorksTM SY89430V
TIMING DIAGRAM
S_DATA
S_CLOCK tSET-UP S_LOAD tSET-UP M[8:0] N[1:0]
tHOLD
P_LOAD tSET-UP
tHOLD
PRODUCT ORDERING CODE
Ordering Code SY89430VJC SY89430VJCTR SY89430VZC SY89430VZCTR Package Type J28-1 J28-1 Z28-1 Z28-1 Operating Range Commercial Commercial Commercial Commercial
7
Micrel
ClockWorksTM SY89430V
28 LEAD SOIC .300" WIDE (Z28-1)
Rev. 02
8
Micrel
ClockWorksTM SY89430V
28 LEAD PLCC (J28-1)
Rev. 03
MICREL-SYNERGY
TEL
3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
FAX
+ 1 (408) 980-9191
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated
9

▲Up To Search▲

Price & Availability of SY89430

	To Download SY89430 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .